PWAOT0=0, PWBOT1=0, OUT_TRIG_EN=0, TRGFRQ=0
Output Trigger Control Register
OUT_TRIG_EN | Output Trigger Enables 0 (0): PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 1 (1): PWM_OUT_TRIGx will set when the counter value matches the VALx value. |
TRGFRQ | Trigger frequency 0 (0): Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 1 (1): Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. |
PWBOT1 | Output Trigger 1 Source Select 0 (0): Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 1 (1): Route the PWM1 output to the PWM_OUT_TRIG1 port. |
PWAOT0 | Output Trigger 0 Source Select 0 (0): Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 1 (1): Route the PWM0 output to the PWM_OUT_TRIG0 port. |